Seminario Nº 54 A robust PLL Algorithm To Achieve Synchronized Gating Patterns in Static Power Converters that Operate in Polluted AC System El Jueves 23 de marzo el Doctor Marcelo Perez mostrará en nuestras dependencias una interesante propuesta de PLL digital. Resultados experimentales ilustran su novedosa propuesta.
Marcelo Pérez was born in Concepción, Chile in 1976. He received
the Eng. degree in electronic engineering, the M. Sc. and the D.Sc in
electrical engineering from the Universidad de Concepción,
Concepción, Chile, in 2000, 2003 and 2006 respectively.
| | | Onda con ruido y onda generada con el PLL
The synchronization of the power converters with the supply
network is an important topic, specially when the control is made
in digital form, like for example, a digital signal processor
(DSP).
The phase locked loop is used in power converter applications to
produce the synchronization of the control system with a
three-phase voltage supply like a STATCOM, single-phase voltage supply like a ballast
or photovoltaic generation systems. Also it is used like a pulse detector, embedded
to the control system
or the power system.
The power system can use a PLL implemented in a analog IC
or digital IC. But, when a digital signal
processor DSP is used the software implementation is preferred.
There are two variations in the software implementation, the zero
cross detection and dq transformation. The first alternative is very sensitive to
signal noise, but interestingly a modifications in the sample time
are developed. The dq transformation it
preferred in three-phase systems and allows to
find the phase and amplitude of the input signal. This method have been studied
in the point of view of unbalance systems, but in general, the sample time is fixed
and is not adjust to have a constant number of samples. Generally, this problem is
overcome using a
small sampling time, restricting the control complexity
implementation.
The main problem of the digital implemented PLLs is that the
number of samples per period is fixed so that the sampled waveform
are in stationary state and does not present noise by the movement
of sampling point, producing a jittering equal to the sample time.
In this work a software-based appears loop phase locked
whose implementation is simple and allows to fit the time of
sampling of the control routine so that besides to synchronize the
signals with the feeding voltage fit a number of samples
determined within a period of network. |